#
# Clocks
#
define_clock   -name {clk}  -freq 50.000 -clockgroup default_clkgroup
define_clock   -name {pci_clk}  -freq 45.000 -clockgroup pci_clkgroup

#
# Clock to Clock
#

#
# Inputs/Outputs
#
define_output_delay -disable     -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
define_input_delay -disable      -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
define_output_delay      -default  12.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
define_input_delay       -default  15.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
define_input_delay      {pci_rst}  0.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}

#
# Registers
#

#
# Multicycle Path
#

#
# False Path
#

#
# Delay Path
#

#
# Attributes
#
define_global_attribute          syn_useioff {1}
#define_attribute          {erx_clk} syn_noclockbuf {1}
#define_attribute          {etx_clk} syn_noclockbuf {1}

#
# Compile Points
#

#
# Other Constraints
#
